1. Technical Field
The present invention relates to memory chips and computer systems in general, and more particularly to a memory system with adaptable redundancy for correcting defective memory cells.
2. Background Art
With the increase in size of produced memory chips, along with the decrease in size of the components on each chip, yield has become a major issue to chip manufacturers.
To increase that yield, manufacturing facilities have been improved by installing cleaner and less vibration-sensitive production tooling, and by applying specific mass-production techniques.
For the same purpose, on-chip redundancy techniques have also been used. Such techniques consist of developing, implementing and manufacturing on-chip `extra` circuitry, which is capable of handling some of the functions normally performed by regular circuitry, if needed. The need arises when test results indicate that part of the regular circuitry is affected by manufacturing defects, and that one or a few functions, that can be isolated from the chip overall functionally, cannot be performed. The extra circuitry is used to functionally replace and correct the defective parts of the regular circuitry.
The choice of the amount of extra circuitry is critical because it decreases the amount of area for the regular circuitry. If both the amount of extra circuitry and the overall area of the chip are increased, more defects in the regular circuitry might be corrected, but at the same time chances are higher that there will be a manufacturing defect within the extra circuitry.
The redundancy technique is well-known in the prior art and can for example be found in U.S. Pat. No. 3,753,244 filed Aug. 18th, 1971, `Yield Enhancement Redundancy Technique`, IBM Technical Disclosure Bulletin, Vol.32, No 8A, Jan. 1990, p.75 and 76, "Redundant/Normal Clock Generation For Redundant Word Line Addressing." These techniques are applied to memory chips and systems which basically feature a memory array, composed of a large plurality of memory cells organized in rows and columns, selectable through address decoding means either for reading the cell content or for writing it.
A typical memory system with redundant circuitry as taught by any of the two above cited prior art documents is shown in FIG. 1. For the sake of clarity and ease of explanation, neither the memory array itself nor the address decoding means for the selection of a column in the memory array (according to the binary value of the address incoming on bus 103) are shown. Address decoding means (100) selects one of the rows R.sub.1 to R.sub.2 (n+1) (n being a positive integer) in the memory array, according to the binary value of address A.sub.0,A.sub.1, . . . A.sub.n incoming on bus 102. As is well-known in the art, a row is selected when an active signal is propagated along a lead from the decoder corresponding to that row, making it possible to access the memory cells within that row for reading or writing their content. Therefore, the expressions `select a row` and `activation signal on lead` will be used interchangeably hereunder, and the reference `R.sub.1 to R.sub.2 (n+1)` will apply to both the rows and their corresponding leads.
In block 100 there are 2.sup.(n+1) identical blocks 101, which constitute the output driver sections of each decoder corresponding to each row, for physically driving the activation signal on one of the leads R.sub.1 to R.sub.27(n+1). This output driver circuit can be quite often a single driver or inverter.
The redundant address decoder circuitry is composed of blocks 105 and 106, and their associated input and output signals. A `FUSE CORPORATOR` 105, is able to select a redundant row RR.sub.1, when the binary value of address A.sub.0,A.sub.1, . . . A.sub.n on bus 102 matches the binary value provided by fuses f.sub.0,f.sub.1, . . . f.sub.n on bus 104. When at least one memory cell within one of the rows R.sub.1 to R.sub.2 (n+1) appears to be defective, the binary value for the address corresponding to that row can be set to the fuses f.sub.0,f.sub.1, . . . f.sub.n in any manner known in the art, (laser fuse blow, electrical fuse blow, EEPROM, etc.). Fuses f.sub.0,f.sub.1, . . . f.sub.n can be selectively blown to be set to a value `0` or `1`. When an attempt is made to read or write the content of any of the memory cells within the faulty row, the redundant row is selected in its place, and the content of one of the redundant memory cells is read or written.
Block 106 `NORMAL ROW SELECTION ENABLE` ensures that there cannot be any simultaneous selection of one of the rows R.sub.1 to R.sub.2 (n+1), and the redundant row RR.sub.1.
Control signal on lead 107 `CLK` controls and synchronizes the whole memory system operation in a manner well-known in the art.
Such an implementation of the redundant circuitry has the main following drawbacks:
When a redundant access occurs (i.e. the binary value for A.sub.0,A.sub.1, . . . A.sub.n corresponds to the binary value of fuses f.sub.0,f.sub.1, . . . f.sub.n), there are two `racing` parallel active paths in the memory system: one through blocks 100 and 101, and the other through blocks 105 and 106. Only the signal output by block 106 can prevent the redundant row RR.sub.1 and one of the rows R.sub.1 to R.sub.2 (n+1) from being selected at the same time. Therefore, extra care is necessary in the design of blocks 105 and 106, as well as in their layout on a chip, to ensure that the signal output by block 106 will, in any case, be faster than any signal within block 100 that might select one of the rows R.sub.1 to R.sub.2 (n+1). PA1 The layout of blocks 105 and 106 is not repetitive and breaks the regular layout of the memory array (not shown) and decoding circuitry (blocks 100 and 101), but still needs to be optimized so as to require as little chip extra space as possible. The layout is intricately dependent on the choice of implemented redundant circuitry, and cannot be easily adapted to any other circuitry. For example, a second redundant row cannot be easily provided, should it be necessary. PA1 Moreover, current memory systems are quite often only sub-parts of a chip; a chip designer picks from a library of available macro functions a memory system of the desired capacity and organization (number of bits per word). To make those macro functions available, one needs to develop a `growable` memory system, i.e. a memory system that is easily adjustable to any kind of capacity and organization as required by the chip designer, including adaptable redundant circuitry.